1. Field of the Invention
The present invention relates to charge pump circuits in semiconductor integrated circuits, and more specifically, to charge pump circuits with minimal output voltage losses and less stress on gate oxides of the MOS devices in the circuits.
2. Discussion of the Related Art
It is now usual to employ charge pump circuits in nonvolatile memories, for the purpose of preparing high voltages to conduct internal operations such as programming and erasing thereof. The charge pump circuits generate operational voltages higher than a power supply voltage provided from the external into the nonvolatile memory chips, by which the operational voltages induce charge tunneling effects through thin gate oxides in programming and erasing cell data.
Since the switched capacitor type of application in analog circuits, it has been mostly used the way of charge pump that was proposed by J. Dickson in IEEE Journal of Solid-State Circuits published on June 1976 (Vol. 11, pp. 374-378), entitled xe2x80x9cOn-chip high voltage generation in NMOS integrated circuits using an improved voltage multiplier technique.xe2x80x9d
The Dickson""s architecture is a construction of diode-coupled switches and pumping capacitors responding to two-phase clock signals. But, it has been well known that pumping circuits based on the Dickson""s architecture fails to provide sufficient pumping when a power supply voltage becomes low, in which their output gains for boosting voltages decrease to an unusable condition.
The circuit shown in FIG. 1 is one of trials to overcome the problems of the circuits based on the Dickson""s architecture, disclosed in IEEE Journal of Solid-State Circuits on April 1998 (Vol. 33, pp. 592-597) by J. T. Wu and K. L. Chang), entitled xe2x80x9cMOS charge pumps for low-voltage operation.xe2x80x9d
Referring to FIG. 1, a first charge transfer switch T11 is connected between an input terminal and a node Q12. The first charge transfer switch T11 responds to a power supply voltage Vcc from the input terminal and a voltage at a node Q11. A first NMOS transistor N11 is connected between the power supply voltage Vcc and the node Q11, and responds to a voltage at the node Q12. A first PMOS transistor P11 is connected between the node Q11 and a node Q14, and responds to the voltage at the node Q12. The bulk terminal of the first PMOS transistor P11 is connected to the node Q14. A first capacitor C11 is connected between a clock terminal and the node Q12, and responds to a clock signal xcfx86 from the clock terminal to charge the node Q12.
A second charge transfer switch T12 is connected between the nodes Q12 and Q14, and responds to the voltage at the node Q12 and a node Q13. A second NMOS transistor N12 is connected between the nodes Q12 and Q13, and responds to a voltage at the node Q14. A second PMOS transistor P12 is connected between the node Q13 and a node Q16, and responds to the voltage at the node Q14. The bulk terminal of the second PMOS transistor P12 is connected to a node Q16. Also, a second capacitor C12 is connected between a clock bar terminal and the node Q14, and responds to a clock bar signal xcfx86B from the clock bar terminal to charge the node Q14.
A third charge transfer switch T13 is connected between the nodes Q14 and Q16, and responds to a voltage at the node Q14 and a node Q15. A third NMOS transistor N13 is connected between the nodes Q14 and Q15, and responds to a voltage at the node Q16. A third PMOS transistor P13 is connected between the node Q15 and a node Q17, and responds to the voltage at the node Q16. The bulk terminal of the third PMOS transistor P13 is connected to a node Q17. Also, a third capacitor C13 is connected to the clock terminal and the node Q16, and responds to the clock signal xcfx86 from the clock terminal to charge the node Q16.
A fourth charge transfer switch T14 is connected to the node Q16 and an output terminal Vout, and responds to the voltages at nodes Q16 and Q17. A capacitor C14 is coupled between the node Q17 and the clock bar terminal, and responds to a clock bar signal xcfx86B from the clock bar terminal. A capacitor C15 is coupled between the output terminal Vout and a ground voltage terminal Vss.
In the operation of the charge pump circuit shown in FIG. 1, when the clock signal xcfx86 is LOW and the clock bar signal xcfx86B is HIGH, the voltage at the node Q12 is set to be a voltage lower than Vcc, and the voltages at the nodes Q14 and Q16 are set to Vcc+2xcex94V (xcex94V is a voltage increment). Meanwhile, the node Q17 maintains a voltage of xcex94V. Since the voltage at the node Q12 is lower than Vcc and the voltage at the node Q14 is Vcc+2xcex94V, the PMOS transistor P11 is turned ON and the voltage at the node Q11 is set at Vcc+2xcex94V. In the meantime, as the voltage at the node Q12 is held to be the voltage lower than Vcc, the NMOS transistor N11 is turned OFF. Since the voltage at the node Q11 is Vcc+2xcex94V, the charge transfer switch T11 is turned ON. Thus, the node Q12 maintains the voltage lower than Vcc.
To the contrary, when the clock signal xcfx86 is HIGH and the clock bar signal xcfx86B is LOW, the voltages at the nodes Q12 and Q14 are set to Vcc+xcex94V and the node Q16 rises up to Vcc+3xcex94V. While the voltage at the node Q12 turns the NMOS transistor N11 ON, the charge transfer switch T11 is turned OFF because the voltage of the node Q12 (i.e., Vcc+xcex94V) is higher than Vcc. At this time, the PMOS transistor P11 is turned OFF. In the meantime, as the voltages at the nodes Q14 and Q16 are held at Vcc+xcex94V and Vcc+3xcex94V, respectively, the PMOS transistor P12 is turned ON to make the voltage of the node Q13 at Vcc+3xcex94V. And, the NMOS transistor N12 is turned OFF because the voltages at the nodes, Q12 and Q14, are identical each other. The voltage at the node Q13 being Vcc+3xcex94V turns the charge transfer switch T12 ON. Thus, the node Q14 maintains Vcc+xcex94V.
Therefore, the nodes, Q12 and Q16, are established respectively on Vcc+xcex94V and Vcc+3xcex94V by means of pumping in response to the clock signal xcfx86 being HIGH, while the node Q14 is pumped up to Vcc+2xcex94V in response to the clock bar signal xcfx86B being HIGH. That is, the clock signal xcfx86 and the clock bar signal xcfx86B, alternately oscillate to maintain the output voltage at Vout at Vcc+3xcex94V.
As described above, in the conventional charge pump circuit, a front charge transfer switch responds to a high voltage generated from subsequent charge transfer switches. Therefore, in contrast to the circuits based on the Dickson""s architecture, the less is the propagation loss for a pumping voltage, the better is the pumping efficiency of the circuit.
However, the conventional charge pump circuit shown in FIG. 1 inevitably faces problems of a high voltage stress at gate oxide films of the MOS devices forming the charge transfer switches because the gate electrodes of the front charge transfer switches are driven by the high voltages generated from subsequent charge transfer switches. For instance, the charge transfer switch T12 is turned on by the voltage of Vcc+3xcex94V at the node Q16, and thereby transfers the voltage of Vcc+xcex94V at the node Q12 to the node Q14. At this time, a high voltage difference of 2xcex94V is between the nodes Q16 and Q12 and applied to gate oxide layers of the MOS devices of the charge transfer switch T12. Such a high voltage stress is disadvantageous to the reliability of the MOS devices.
Furthermore, as the MOS transistor acting T14 as a transmission switch for the output terminal Vout is formed in a diode circuit, there is a voltage drop when a voltage level at the node Q16 is transmitted to the output voltage Vout. Such a voltage drop is also disadvantageous to the reliability of the MOS devices.
Accordingly, the present invention is directed to a charge pump circuit that substantially obviates one or more of the problems due to limitations and disadvantages of the related art.
An object of the present invention is to provide a charge pump circuit capable of driving a higher pumping voltage without degrading the reliability of MOS devices.
Another object of the present invention is to provide a charge pump circuit enhancing the efficiency of a voltage pumping operation, increasing an output voltage gain.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
To achieve these and other advantages and in accordance with the purpose of the present invention, as embodied and broadly described, the charge pump circuit includes a first switch for selectively connecting an input terminal to a second pumping node; a second switch for selectively connecting the input terminal to a first pumping node; a first pumping capacitor for boosting a signal at the second pumping node in response to a first clock signal; a second pumping capacitor for boosting a signal at the first pumping node in response to a second clock signal; a third switch for selectively connecting the second pumping node to an output terminal; a fourth switch for selectively connecting the first pumping node to the output terminal; and a fifth switch for regulating the third switch in response to a voltage level of the signal at the first pumping node.
In another aspect, the charge pump circuit includes a first NMOS transistor having a drain terminal connected to an input terminal, a gate terminal connected to a first pumping node and a source terminal connected to a second pumping node; a second NMOS transistor having a drain terminal connected to the input terminal, a gate terminal connected to the second pumping node and a source terminal connected to the first pumping node; a first PMOS transistor having a source terminal connected to the second pumping node, a gate terminal connected to the first pumping node and a drain terminal connected to an output terminal; a second PMOS transistor having a source terminal connected to the first pumping node, a gate terminal connected to the second pumping node and a drain terminal connected to the output terminal; a third PMOS transistor having a source terminal connected to the second pumping node, a gate terminal connected to the first pumping node and a drain terminal connected to a bulk terminal of the first PMOS transistor; a fourth PMOS transistor having a source terminal connected to the first pumping node, a gate terminal connected to the second pumping node and a drain terminal connected to a bulk terminal of the second PMOS transistor; a first pumping capacitor for boosting a signal at the second pumping node in response to a first clock signal; and a second pumping capacitor for boosting a signal at the first pumping node in response to a second clock signal, wherein the first and second clock signals being complementary in phase each other, and wherein the second NMOS transistor, and the second and fourth PMOS transistors are driven in response to a voltage level of the first pumping node while the first NMOS transistor, and the first and third PMOS transistors are driven in response to a voltage level of the first pumping node.
In yet another aspect, the charge pump circuit includes a first NMOS transistor having a drain terminal connected to an input terminal, a gate terminal connected to a first pumping node and a source terminal connected to a second pumping node; a second NMOS transistor having a drain terminal connected to the input terminal, a gate terminal connected to the second pumping node and a source terminal connected to the first pumping node; a third NMOS transistor having a source terminal connected to a bulk terminal of the first NMOS transistor, a gate terminal connected to the first pumping node and a drain terminal connected to the second pumping node; a fourth NMOS transistor having a source terminal connected to a bulk terminal of the second NMOS transistor, a gate terminal connected to the second pumping node and a drain terminal connected to the first pumping node; a first PMOS transistor having a source terminal connected to the second pumping node, a gate terminal connected to the first pumping node and a drain terminal connected to an output terminal; a second PMOS transistor having a source terminal connected to the first pumping node, a gate terminal connected to the second pumping node and a drain terminal connected to the output terminal; a third PMOS transistor having a source terminal connected to the second pumping node, a gate terminal connected to the first pumping node and a drain terminal connected to a bulk terminal of the first PMOS transistor; a fourth PMOS transistor having a source terminal connected to the first pumping node, a gate terminal connected to the second pumping node and a drain terminal connected to a bulk terminal of the second PMOS transistor; a first pumping capacitor for boosting a signal at the second pumping node in response to a first clock signal; and a second pumping capacitor for boosting a signal at the first pumping node in response to a second clock signal, wherein the first and second clock signals being complementary in phase each other, and wherein the second and fourth NMOS transistors, and the second and fourth PMOS transistors are driven in response to a voltage level of the second pumping node while the first and third NMOS transistors, and the first and third PMOS transistors are driven in response to a voltage level of the first pumping node.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.